veriflow-cc

Name: veriflow-cc Review
Item: veriflow-cc
Rating: 2.3
Author: Aaron Matthews

Skill Infrastructure Poor

Works inClaude Code

Poor Scanned — metadata only

Reduces RTL design iteration cycles by automating the path from architecture specification to synthesizable Verilog, cutting manual coding and verification l…

VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.

Generate RTL from natural-language architecture specs, validate with iVerilog
Auto-synthesize Verilog designs to gate-level with Yosys, catch timing early
Iterate on behavioral requirements without rewriting test benches manually

38 starsFreeQuick setup

Below standard — Significant caveats apply. Not recommended without careful review of the security and evaluation sections.

Why it matters

Reduces RTL design iteration cycles by automating the path from architecture specification to synthesizable Verilog, cutting manual coding and verification loops. Embeds formal behavioral verification directly in the generation pipeline.

Best for

Hardware engineers and chip design teams who need rapid prototyping of digital logic blocks without manually writing and debugging Verilog at each stage.

Works in

Claude Code Claude Cowork Claude Chat

Source

https://github.com/bjwanneng/veriflow-cc

By bjwanneng

How to Get It

Option 1: Claude Desktop App (Code Mode)Click the + button next to the prompt box → Plugins → Add plugin. Search and click Install. Skills work in Claude Code only.

Option 2: Paste into Claude CodeCopy the command below and paste it into your conversation. Claude will install it.

Command

claude plugins install bjwanneng/veriflow-cc

Tip: Paste this into a Claude Code conversation. Verify command matches your Claude Code version.

Auto-generated from the tool's public listing — not hands-on verified. Cross-check against the source repo's README before running.

First thing to try

After installing, paste this into Claude:

Help me generate RTL from natural-language architecture specs, validate with iVerilog

CostFree

Trust Signals Auto-scanned

Stars38Contributors3Last updated2026-07-09Known CVEsNone foundSources: GitHub Advisory Database + OSV.dev · Scanned 2026-07-25 · scanner v1

Community Pulse Quiet

No community discussions found yet. This doesn't mean the tool isn't good — it may be new or serve a niche use case.

Reviewer notes

Auto-scanned review. These are observations, not a security certification.

Scored from trust signals (evidence-eval-v1): 38 GitHub stars; 3 contributors; last commit 16d ago; license no license.

Things to check

Scanned, not hands-on tested — this entry was auto-scanned from public metadata (GitHub metrics, license, security flags). No reviewer has run it, and no tool-specific limitations have been documented yet.

How to evaluate tools before deploying →

Data shown here comes from public APIs and automated scanning. Reviewer notes reflect one person's experience. This is not a security certification or legal recommendation. Always evaluate tools according to your own organization's policies.

Evaluation Scores

Evaluation

Ease of Use

1/5

Versatility

2/5

Reliability

4/5

Security

3/5

Overall score2.30 / 5.00 PoorEvaluatedJul 2026

Scored from trust signals (evidence-eval-v1): 38 GitHub stars; 3 contributors; last commit 16d ago; license no license.

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