veriflow-cc
VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.
https://github.com/bjwanneng/veriflow-cc
By bjwanneng
How to Get It
claude plugins install bjwanneng/veriflow-cc
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